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Integrated Circuit Systems, Inc.
ICS9248-195
Frequency Generator & Integrated Buffers for PENTIUM II/IIITM & K6
Recommended Application: Key Specifications: * CPU Output Jitter @ 2.5V: <300ps 440BX, MX, VIA PM/PL/PLE 133 style chip set, with * CPU Output Jitter @ 3.3V: <250ps Coppermine or Tualatin processor, for note book * PCI Output Jitter @ 3.3V: <250ps applications. * CPU Output Skew @ 2.5V: <175ps Output Features: * CPU Output Skew @ 3.3V: <175ps * 4 - CPUs @ 2.5V/3.3V * PCI Output Skew @ 3.3V: <500ps including 1 free running CPUCLK_F * PCI Early to PCI Skew @ 3.3V: typ = 3ns * 9 - SDRAM @ 3.3V * SDRAM Output Skew @ 3.3V: <500ps * 7 - PCI @ 3.3V, including 1 free running PCICLK_F * 1 - PCI Early @ 3.3V Pin Configuration * 1 - 48MHz, @ 3.3V fixed. 48 REF1/FS2* VDDREF 1 47 VDDLCPU *SPREAD/REF0 2 * 1 - 24/48MHz @ 3.3V 46 CPUCLK_F GNDREF 3 * 2 - REF @3.3V, 14.318MHz. 45 CPUCLK0 4 X1 44 GNDLCPU 5 X2 Features: 43 CPUCLK1 6 VDDPCI 42 CPUCLK2 7 *CPU2.5_3.3#/PCICLK_F * Up to 137MHz frequency support 41 CLK_STOP# 8 *FS3/PCICLK0 40 GNDSDR 9 GNDPCI * 97MHz to support high-end AMD processor. 39 SDRAM_F 10 *SEL24_48#/PCICLK1 * Support power management: CLK, PCI, stop and 38 SDRAM0 11 *SELPCIE_6#/PCICLK2 2 37 SDRAM1 12 PCICLK3 Power down Mode from I C programming. 36 VDDSDR 13 PCICLK4 35 * Spread spectrum for EMI control SDRAM2 14 VDDPCI 34 SDRAM3 15 BUFFER IN * Uses external 14.318MHz crystal 33 GNDSDR 16 GNDPCI 32 SDRAM4 17 PCICLK5 * FS pins for frequency select 31 SDRAM5 18 PCICLK6/PCICLK_E
ICS9248-195
VDDCOR PCI_STOP# *Vtt_PWRGD/PD# GND48 SDATA SCLK
19 20 21 22 23 24
30 29 28 27 26 25
VDDSDR SDRAM6 SDRAM7 VDD48 48MHz/FS0* 24_48MHz/FS1*
Block Diagram
48-Pin SSOP and TSSOP
* Internal Pull-up Resistor of 120K to VDD
Functionality
Bit2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPUCLK 66.67 100.00 66.67 133.33 66.67 100.00 100.00 133.33 66.67 100.00 90.00 133.33 70.00 105.00 133.33 140.00 PCICLK 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 30.00 33.33 35.00 35.00 33.33 35.00
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ICS9248-195
Pin Descriptions
PIN NUMBER 1 2 20 3, 9, 16, 33, 40, 44 4 5 6,14 7 8 10 11 17, 13, 12 15 18 19 PIN NAME VDDREF S P R E A D 1,2 REF0 PCI_STOP# GND X1 X2 VDDPCI C P U 2 . 5 _ 3 . 3 # 1,2 PCICLK_F FS31,2 PCICLK0 SEL24_48#1,2 PCICLK1 SELPCIE_6#1,2 PCICLK2 PCICLK (5:3) BUFFER IN PCICLK6/PCICLK_E VDDCOR Vtt_PWRGND 21 PD#1 22 28, 29, 31, 32, 34, 35, 37, 38 30, 36 23 24 25 26 27 39 41 42, 43, 45 46 47 48 GND48 SDRAM (7:0) VDDSDR SDATA SCLK 24_48MHz FS11, 2 48MHz FS01, 2 VDD48 SDRAM_F CLK_STOP# CPUCLK (2:0) CPUCLK_F VDDLCPU REF1 FS21, 2 IN PWR OUT PWR IN IN OUT IN OUT IN PWR OUT IN OUT OUT PWR OUT IN TYPE PWR IN OUT IN PWR IN OUT PWR IN OUT IN OUT IN OUT IN OUT OUT IN OUT PWR IN DESCRIPTION Ref, XTAL power supply, nominal 3.3V Active High Spread Spectr um enable input. Power-up default is "High", spreading is "on" 14.318 Mhz reference clock.This REF output is the STRONGER buffer for ISA BUS loads Halts PCICLK clocks at logic 0 level, when input low (In mobile mode, MODE=0) Ground Cr ystal input, has inter nal load cap (36pF) and feedback resistor from X2 Cr ystal output, nominally 14.318MHz. Supply for PCICLK_F and PCICLK nominal 3.3V Indicates whether VDDLCPU is 2.5 or 3.3V. High=2.5V CPU, LOW=3.3V CPU. Latched Input. Free running PCI clock not affected by PCI_STOP# for power management. Frequency select pin. Latched Input. PCI clock output. Synchronous to CPU clocks with 1-4ns skew (CPU early) Selects either 24 or 48MHz when Low =48 MHz PCI clock output. Synchronous to CPU clocks with 1-4ns skew (CPU early) PCI Early or normal PCI select latch input. (for pin 18 power-up default is "High" early PCICLK.) PCICLK clock output. PCI clock outputs. Synchronous to CPU clocks with 1-4ns skew (CPU early) Input to Fanout Buffers for SDRAM outputs. PCI clock output or ear ly PCI clock output selectable by SELPCIE_6# Power pin for the PLL core. 3.3V This pin acts as a dual function input pin for Vtt_PWRGD and PD# signal. When Vtt_PWRGD g o e s h i g h t h e f r e q u e n c y s e l e c t w i l l b e l a t c h e d a t p ow e r o n t h e r e a f t e r t h e p i n i s a n asynchronous active low power down pin. Asynchronous active low input pin used to power down the device into a low power state. The inter nal clocks are disabled and the VCO and the cr ystal are stopped. The latency of the p ow e r d ow n w i l l n o t b e g r e a t e r t h a n 4 m s. Ground pin for the 24 & 48MHz output buffers & fixed PLL core. SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin (controlled by chipset). Supply for SDRAM and CPU PLL Core, nominal 3.3V. Data input for I2C serial input, 5V tolerant input Clock input of I2C input, 5V tolerant input 24MHz or 48MHz output clock selectable by pin 10 Frequency select pin. Latched Input. 48MHz output clock Frequency select pin. Latched Input Power for 24 & 48MHz output buffers and fixed PLL core. Free running SDRAM clock output. Not affected by CPU_STOP# This asynchronous input halts CPUCLK, & SDRAM at logic "0" level when driven low. CPU clock outputs, powered by VDDLCPU Free running CPU clock. Not affected by the CPU_STOP# Supply for CPU clocks 2.5V 14.318 MHz reference clock. Frequency select pin. Latched Input
Notes: 1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low.
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ICS9248-195
General Description
The ICS9248-195 is the single chip clock solution for Notebook designs using the 440BX, MX, VIA PM/PL/PLE 133 style chip set, with Coppermine or Tualatin processor, for Note book applications. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248195 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit Bit 7 Description 0 = Center Spread Spectrum Modulation 1 = Down Spread Spectrum Modulation FS3 FS2 FS1 FS0 CPUCLK Bit2 Bit6 Bit5 Bit4 PCICLK Center Spread % Down Spread% PWD 1
Bit 2, 6:4
Bit 3 Bit 1 Bit 0
0 0 0 0 66.67 33.33 0.35% -0.70% 0 0 0 1 100.00 33.33 0.35% -0.70% 0 0 1 0 66.67 33.33 0.60% -1.20% 0 0 1 1 133.33 33.33 0.35% -0.70% 0 1 0 0 66.67 33.33 0.23% -0.45% 0 1 0 1 100.00 33.33 0.23% -0.45% 0 1 1 0 100.00 33.33 0.60% -1.20% 0 1 1 1 133.33 33.33 0.23% -0.45% 1 0 0 0 66.67 33.33 0.45% -0.90% 1 0 0 1 100.00 33.33 0.45% -0.90% 1 0 1 0 90.00 30.00 0.35% -0.70% 1 0 1 1 133.33 33.33 0.45% -0.90% 1 1 0 0 70.00 35.00 0.35% -0.70% 1 1 0 1 105.00 35.00 0.35% -0.70% 1 1 1 0 133.33 33.33 0.60% -1.20% 1 1 1 1 140.00 35.00 0.35% -0.70% 0 - Frequency is selected by hardware select pins. Latched inputs. 1 - Frequency is controlled by I2C programming. 0 - Normal 1 - Spread Spectrum Enabled 0 - Running 1 - Tristate all outputs
Note1 0011
0 1 0
Notes: 1, Default at Power-up will be for latched logic inputs to define frequency. Bit [2, 6:4] are default to 0011. 2, PWD = Power-Up Default
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ICS9248-195
Byte 1: Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 46 39 42 43 45 PWD 1 1 0 0 1 1 1 1 Description (Reserved) CPUCLK_F (En/Dis) (Reserved) (Reserved) SDRAM_F (En/Dis) CPUCLK2 (En/Dis) CPUCLK1 (En/Dis) CPUCLK0 (En/Dis)
Byte 2: Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 7 18 17 13 12 11 10 8 PWD 1 1 1 1 1 1 1 1 Description PCICLK_F (En/Dis) PCICLK6 (En/Dis) PCICLK5 (En/Dis) PCICLK4 (En/Dis) PCICLK3 (En/Dis) PCICLK2 (En/Dis) PCICLK1 (En/Dis) PCICLK0 (En/Dis)
Byte 3: Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 28 29 31 32 PWD 1 0 0 0 1 1 1 1 Description (Reserved) (Reserved) (Reserved) (Reserved) SDRAM7 (En/Dis) SDRAM6 (En/Dis) SDRAM5 (En/Dis) SDRAM4 (En/Dis)
Notes: 1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched register values will be inverted from pin values. Default latch condition is for all latched inputs to be floating (pulled up via internal resistor) at power-up.
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ICS9248-195
Byte 4: Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # PWD 1 0 0 0 0 0 0 1 Description (Reserved) (Reserved) (SEL24_48)# Latched FS0# Latched FS1# Latched FS2# Latched FS3# (Reserved)
Byte 5: Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 34 35 37 38 26 25 48 2 PWD 1 1 1 1 1 1 1 1 Description SDRAM3 (En/Dis) SDRAM2 (En/Dis) SDRAM1 (En/Dis) SDRAM0 (En/Dis) 48MHz (En/Dis) 24MHz (En/Dis) REF1 (En/Dis) REF0 (En/Dis)
Notes: 1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched register values will be inverted from pin values. Default latch condition is for all latched inputs to be floating (pulled up via internal resistor) at power-up.
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ICS9248-195
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . 5.5 V GND -0.5 V to VDD +0.5 V 0C to +70C 115C -65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Operating Supply Current Powerdown Current Input Frequency Input Capacitance1 Clk Stabilization1 Skew1
1
SYMBOL VIH VIL IDD3.3OP I DDPD Fi CIN CINX TSTAB tCPU-PCI1
CONDITIONS
MIN TYP 2 V SS - 0.3
CL = 0 pF; Select @ 66MHz CL = 0 pF; Select @ 100MHz CL = 0 pF; Select @ 133MHz CL = 0 pF; Input address VDD or GND VDD = 3.3 V Logic Inputs X1 & X2 pins From V DD = 3.3 V to 1% target Freq. VT = 1.5 V 27 1
MAX UNITS VDD + 0.3 V 0.8 V 150 mA 170 180 A 600 14.32 MHz 5 45 5.5 4 pF pF ms ns
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER Operating SupplyCurrent Powerdown Current Skew1
1
SYMBOL IDDL2.5 IDDLPD tCPU-PCI2
CONDITIONS CL = 0 pF; Select @ 66.8 MHz CL = 0 pF; Select @ 100 MHz CL = 0 pF; Select @ 133 MHz
CL = 0 pF; Input address VDD or GND
MIN
TYP
V T = 1.5 V; V TL = 1.25 V
1
MAX 15 18 25 10 4
UNITS mA mA ns
Guaranteed by design, not 100% tested in production.
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ICS9248-195
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20 pF PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time1 Duty Cycle Skew window1 Jitter, Cycle-to-cycle1
1 1
SYMBOL VOH2A VOL2A I OH2A IOL2A tr2A tf2A dt2A tsk2A tjcyc-cyc2A
CONDITIONS IOH = -20 mA IOL = 12 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, V OL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 2.4
TYP
22 1.35 45 1.44 50.3 70 160
MAX UNITS V 0.4 V -27 mA mA 2 2 55 175 250 ns ns % ps ps
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPU
TA = 0 - 70C; V DDL = 2.5 V +/-5%; CL = 20 pF PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time1 Duty Cycle1 Skew window1 Jitter, Cycle-to-cycle1
1
SYMBOL VOH2B VOL2B IOH2B I OL2B tr2B tf2B dt2B tsk2B tjcyc-cyc2B
CONDITIONS IOH = -12 mA IOL = 12 mA VOH = 1.7 V VOL = 0.7 V VOL = 0.4 V, V OH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V, < 133 MHz VT = 1.25 V, >= 133 MHz VT = 1.25 V VT = 1.25 V
MIN 2
TYP
22 1.40 45 42 1.70 52 51 60 143
MAX UNITS V 0.4 V -21 mA mA 1.8 1.8 55 52 175 250 ns ns % ps ps
Guaranteed by design, not 100% tested in production.
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ICS9248-195
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 30 pF PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time
1 1
SYMBOL VOH1 VOL1 I OH1 I OL1 t r1 t f1 dt1 t sk1 t sk2 t jabs1
CONDITIONS I OH = -18 mA I OL = 9.4 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, V OL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V PCICLKE to PCI [5:0] VT = 1.5 V
MIN 2.4
TYP
38 1.60 1.50 45 2 51.5 380 2.71 120
MAX UNITS V 0.4 V -33 mA mA 2.2 2.2 55 500 4 250 ns ns % ps ns ps
Duty Cycle
Skew window1 Skew window1 Jitter, Absolute1
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 30 pF PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time1 Duty Cycle1 Skew window1 Propagation Time1 (Buffer In to output)
1 1
SYMBOL VOH3 VOL3 I OH3 I OL3 Tr3 Tf3 Dt3 Tsk3 Tsk3
CONDITIONS I OH = -28 mA I OL = 19 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, V OL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 2.4
TYP
32 1.17 1.20 50 210 4.10
42
MAX UNITS V 0.4 V -46 mA mA 1.6 ns 1.6 ns 52 % 250 ps 5 ns
Guaranteed by design, not 100% tested in production.
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ICS9248-195
Electrical Characteristics - 24,48MHz
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time
1 1
SYMBOL VOH5 VOL5 I OH5 I OL5 t r5 t f5 dt5 t CYCLE
CONDITIONS I OH = -14 mA I OL = 6 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, V OL = 0.4 V VT = 1.5 V VT = 1.5 V
MIN 2.4
TYP
16 1.93 2.63 45 50.9 436
MAX UNITS V 0.4 V -20 mA mA 4 4 55 600 ns ns % ps
Duty Cycle Jitter, Absolute1
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time1 Duty Cycle Jitter, cycle to cycle1
1 1
SYMBOL VOH5 VOL5 I OH5 I OL5 tr5 tf5 dt5 t jcycle5
CONDITIONS IOH = -14 mA IOL = 6 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, V OL = 0.4 V VT = 1.5 V VT = 1.5 V
MIN 2.4
16
TYP 2.6 0.22 -32 22 2.11 2.14
MAX UNITS V 0.4 V -20 mA mA 4 4 55 1000 ns ns % ps
45 -600
52.1 848
Guaranteed by design, not 100% tested in production.
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ICS9248-195
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 * ICS clock will acknowledge each byte one at a time. * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ICS (Slave/Receiver)
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK ACK
Dummy Byte Count
ACK Byte Count
ACK
ACK
Byte 0
Byte 0
ACK
ACK
Byte 1
Byte 1
ACK
ACK
Byte 2
Byte 2
ACK
ACK
Byte 3
Byte 3
ACK
ACK
Byte 4
Byte 4
ACK
ACK
Byte 5
Byte 5
ACK
ACK Stop Bit
Stop Bit
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PII/PIII "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
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ICS9248-195
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad 2K W
Via to VDD
8.2K W Clock trace to load Series Term. Res.
Fig. 1
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ICS9248-195
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 4 mS. The power down latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and CLK_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
PD#
CPUCLK
PCICLK VCO Crystal
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device). 2. As shown, the outputs Stop Low on the next falling edge after PD# goes low. 3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
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ICS9248-195
CLK_STOP# Timing Diagram
CLK_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation. CLK_STOP# is synchronized by the ICS9248-195. The minimum that the CPU clock is enabled (CLK_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
INTERNAL CPUCLK PCICLK CLK_STOP# PCI_STOP# (High)
SDRAM CPUCLK CPUCLK _F SDRAM_F
Notes: 1. All timing is referenced to the internal CPU clock. 2. CLK_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPU clocks inside the ICS9248-195. 3. SDRAM-F output is controlled by Buffer in signal, not affected by the ICS9248-195 CLK_STOP# signal. SDRAM are controlled as shown. 4. All other clocks continue to run undisturbed.
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ICS9248-195
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-195. It is used to turn off the PCICLK clocks for low power operation. PCI_STOP# is synchronized by the ICS9248-195 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK clock on latency cycles are only three rising PCICLK clocks, off latency is one PCICLK clock.
CPUCLK (Internal)
PCICLK_F (Internal) PCICLK_F (Free-running) CLK_STOP#
PCI_STOP#
PCICLK
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS9248. 3. All other clocks continue to run undisturbed. 4. CLK_STOP# is shown in a high (true) state.
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N
c
SYMBOL
L
INDEX AREA
E1
E
12 D h x 45
A A1
A A1 b c D E E1 e h L N
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 VARIATIONS D mm. MIN MAX 15.75 16.00
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
-Ce
b SEATING PLANE .10 (.004) C
N 48
10-0034
D (inch) MIN .620 MAX .630
Reference Doc.: JEDEC Publication 95, MO-118
300 mil SSOP Package
Ordering Information
ICS9248yF-195LF-T
Example:
ICS XXXX y F LF- T
Designation for tape and reel packaging Lead Free (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
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N
c
L
INDEX AREA
E1
E
12 D
a
A2 A1
A
In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 D SEE VARIATIONS SEE VARIATIONS E 8.10 BASIC 0.319 BASIC E1 6.00 6.20 .236 .244 e 0.50 BASIC 0.020 BASIC L 0.45 0.75 .018 .030 N SEE VARIATIONS SEE VARIATIONS 0 8 0 8 aaa -0.10 -.004 VARIATIONS N 48
10-0039
-Ce
b SEATING PLANE
D mm. MIN MAX 12.40 12.60
D (inch) MIN .488 MAX .496
aaa C
Ref erence Doc.: JEDEC Publication 95, M O-153
(0.020 mil) (240 mil) 6.10 mm. Body, 0.50 mm. pitch TSSOP
Ordering Information
ICS9248yG-195LF-T
Example:
ICS XXXX y G LF- T
Designation for tape and reel packaging Lead Free (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
0375D--02/02/04
16

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